In many cases, signals assigned to port maps or to other signals are ordinary std_logic_vectors or other simple arrays.
Sigasi knows the type of these signals, since it is displayed in a tooltip when you hoover over the signal. The array indexes are displayed as well, so the size can be determined as well.
For these cases, it would be possible to add a check if the dimensions of the vectors match.
That would help pointing out errors, even before compilation is run.