This is seen in 2.14, unsure if it also existed before.
libraryIEEE;
useIEEE.std_logic_1164.all;
useIEEE.numeric_std.all;
entity test is
endentity;
architecture rtl of test is
type rectype isrecord time_field :time; slv_field :std_logic_vector(7downto0);endrecord;
signal test_rec : rectype;
signal test_time :time:=0ns;
begin
test_time <= to_integer(unsigned(test_rec.slv_field)) * test_rec.time_field;
process
beginwaitfor to_integer(unsigned(test_rec.slv_field)) * test_rec.time_field;--this line is incorrectly mark