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Beautify entire project

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I have to work with the leon, and have difficulties reading it, your beautify function (ctrl shift f) helps quite a lot, however I have to open a file ot apply it. An option to run it on an entire project in eclipse would be great.

(I asked about this on so before: http://stackoverflow.com/questions/18508171/run-eclipse-editor-action-on-entire-project)


adding tcl support fails due to conflicting dependencies (sigasi 2.16)

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Hey everybody,
I tried to install the tcl by consulting this "link:http://www.sigasi.com/content/eclipse-tcl-support-sigasi
It seems like this is intended for sigasi not for sigasi 2.
When i try to install the package i get the following:

Cannot complete the install because of a conflicting dependency.
  Software being installed: Dynamic Languages Toolkit – TCL Development Tools 3.0.0.v20101109-0623-7g--EC3wSgpTPwM02543 (org.eclipse.dltk.tcl.feature.group 3.0.0.v20101109-0623-7g--EC3wSgpTPwM02543)
  Software currently installed: Sigasi 2.16.0.201308231404 (com.siga

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simulator ISIM

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hi,
we have the problem to start the simulator ISIM from the new version of Sigasi (2.16)
It appears the following error message:
Launching ISIM sinulation … has encountered a problem. An internal error occured during: "Launching ISIM simulation …".
java.lang.NullPointerException
We enter the ISE installation path for Isim probably correctly:
C:\Xilinx\13.4\ISE_DS\ISE
it works with the old SIGASI versions (2.13, 2.14) and ModelSim works with Sigasi 2.16
I hope you can help us.
Sincerely,
R.

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Feature request: Highlight inactive code

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Eclipse has the ability to highlight inactive code. Since Sigasi does calculate generics, it should be possible to inactive generate sections such as this

gen_foo :if false generate
foo_inst :entity work.foo;endgenerate gen_foo;

Formatting array-of-vector initialisers

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If I initialise an array of vectors with some function calls, the formatter makes a mess of it:

type uint64_array is array (naturalrange<>)ofunsigned(63downto0);constant data_count_answers : uint64_array(0to3):=(1=> to_unsigned(20, 64),
			2=> to_unsigned(6,64),
			3=> to_unsigned(20, 64),
			others=>(others=>'0'));

comes out as
constant data_count_answers : uint64_array(store'range):=(1=> to_unsigned(20,
				             64),
			2=> to_unsigned(6,
				             64),
			3=> to_unsigned(20,
				             64),
			ot

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Encapsulate concurrent statements

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Has this functionality been removed?

http://www.sigasi.com/documentation/book/structural.html#encapsulate-label

Various Quartus (or even ISE/Vivado?) improvements

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1. Deleting 'referenced' files.
You cannot delete a file in the project: -> Deleting Quartus Project resources is currently not supported
Yet, if you open the .qsf file (In Eclipse itself) and delete the corresponding "set_global_assignment -name VHDL_FILE .." and save the .qsf Hdt will refresh fine. So it can't be that hard. I can live with this 'workaround' for now (and a day).
2. Adding 'existing' files.

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how to add anew library like unisim to sigasi 2

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Dear support,
why is it in sigasi 2 quite difficult to add libraries?
and why can't I reuse the .library.xml to transfer from sigasi 1 to 2:
I'd like to add followng libs in sigasi 2:

<libraryMapper><version>1</version><item library="std" location="resource:/com/sigasi/vhdl/std"/><item library="ieee" location="resource:/com/sigasi/vhdl/ieee"/><item library="ieee" location="resource:/com/sigasi/vhdl/vital2000"/><item excluding="/0_Source/library_files/output_register_32.vhd|/1_Testbench/backplane_tests/PD_D500_A|/1_Testbench/pp_e10x/testbench

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Feature Request: Autocomplete for Record

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Hi,

i use often records.
When i want to define a constant of a record type, there is no autocomplete of the elements.

type reg_type isrecordVCCH_add	:std_logic_vector(7downto0);VCCL_add	:std_logic_vector(7downto0);VCCH_reg	:std_logic_vector(7downto0);VCCL_reg	:std_logic_vector(7downto0)
  constant reset_r : reg_type :=(VCCH_add =>(others=>'0'), VCCL_add =>(others=>'0'), VCCH_reg =>(others=>'0'), VCCL_reg =>(others=>'0'));
 

There is no autocomplete when i type VCCH and then STRG+Space.
Is this possible

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Problem of running top level testbench using Isim

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Hi,

I just downloaded the Sigasi for win 64bit and tried the Integration with Xilinx ISim HDL Simulator using my surface pro. It seems that the isim doesn't work well in win 8 pro. The simulator ran as expected but didn't show anything about the top level test bench file.screen shotscreen shot Any solution for this problem?

Feature Request: System Verilog syntax highlighting

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Hi,

in addition to your Verilog support, is it possible to add System Verilog syntax highlighting as well? We use SV mainly for testbenches. Unfortunately, I cannot open .sv files in Sigasi yet.

Denis

Forum Spam Protection

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Hello Sigasi Team,

Can you please add some spam protection mechanism for this forum? It is annoying if you have enabled the mail notification for a thread you are interested in and get so many mails because of spam messages in it.

Thanks a lot!
Fabian

Feature Request: Declare Signals as an element of a record

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Hi,

i like the qick fix feature "Declare signal" for unknown signals.
Is it also possible, to declare a signal "r.siganl2" as an element of a the corresponding record if the type of the record exists.

type reg_type isrecord
	signal1	:std_logic;endrecord;signal r : reg_type;if r.signal2 ='0'then-- here is the quickfix declare signal, here i need it to declare it as a element of type reg_type

Project not appearing in Project Explorer

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After selecting a workspace to open an existing project, no projects appear under the Project Explorer pane. This project does exist though! I tried rebooting the computer but no luck. My license is set to expire but not for another two days. Could this be the culprit?

~ Melissa

vhpcomp.exe error after updating to 2.18

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After upgrading Sigasi from 2.17 to 2.18, the Isim integration doesn't work anymore. When the project is compiling after saving, the windows message "vhpcomp.exe has encountered a problem and needs to close" appears serveral times.

The console output in Sigasi is:

Deleted work.test
Deleted work.test.RTL
Adding library mapping for work to xilinxsim.ini
C:\DOKUME~1\baumannt\LOKALE~1\Temp\SigasiCompileCache8936944184968922179\test\isim > D:\Xilinx\14.3\ISE_DS\ISE\bin\nt\vhpcomp.exe --incremental -work work D:\VHDL_Workspace\test\test.vhd

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Incorrect Error at use clause for overloaded "=" operator

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Hi,
When declaring some use clauses for overloaded operators (see below), I get an incorrect error on the use clause for the "=" operator.

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Starting ModelSim with a do file from Sigasi

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Hello,
is it possible to start ModelSim direct from Sigasi and run a "do" file?

Sigasi External Tools ConfySigasi External Tools Confy

Invoking ncvhdl

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Hi,

I just installed Sigasi VHDL plugin for eclipse. I would like to know how to configure it so that I can call ncvhdl directly from eclipse. How can it knows the cds.lib and hdl.var file?

Basically, how do I configure the Sigasi and Eclipse to work in vhdl with nvcim?

Thanks,

Claude

Feature request: add an eclipse variable for file library

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Since the included tool integration does not allow to specify additional parameters, the only solution is to use "external tools". To create a compile script for an single file or event a build script for the project it is necessary to have the associated library information per file.
By the way it should be easy for you to add a possibility to add own additional commandline parameters to the automated toolchain integration.

"No entry" sign on source file

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In Sigasi/Eclipse, what's the meaning of the "no entry" sign on a source file:

No EntryNo Entry

Thanks, Guy.

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