Given this file:
library ieee;
use ieee.std_logic_1164.all;
entity bug_test isport( clk :instd_logic; rst :instd_logic; test_one :instd_logic; test_two :instd_logic; test1_out :outstd_logic; test2_out :outstd_logic);
endentity bug_test;
architectureRTLof bug_test is
begin
test1_out <='1'when test_one ='0'and test_two ='1'else'0';
test_proc:process(clk, rst)
beginif rst ='1'then test2_out <='0';elsif rising_edge(clk)thenif test_one ='0'and test