Looks like overloaded functions are not properly resolved when used on the left side of a port map.
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Sigasi - Discussion Forum
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Channel Details:
- Title: Sigasi - Discussion Forum
- Channel Number: 12162370
- Language: English
- Registered On: April 18, 2013, 11:56 am
- Number of Articles: 127
- Latest Snapshot: November 15, 2015, 4:22 pm
- RSS URL: http://www.sigasi.com/forums/support-forum/feed
- Publisher: http://www.sigasi.com/taxonomy/term/123/0
- Description: Issues and general discussions concerning Sigasi for VHDL and Verilog.
- Catalog: //sigasi5.rssing.com/catalog.php?indx=12162370
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