Feature request : load/save color schemes
Hi, Some of us prefer a black background for the editor. You can change all the syntax highlighting, but it is rather tedious. It would be nice if you could just import a color scheme from a colleague....
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Small feature request: unused singal with attribute not flagged
unused declarationJust a small detail: the attribute prevents a declaration from being flagged as 'unused'. Only if the attribute is removed, like in line 454, the expected warning is indicated....
View ArticleWhere are the auto replace options?
I googled but found nothing on this. Where are the options for auto-replacing strings? I'd like to disable '..' -> '<=' since I use '…' a lot in my comments. I'd also like to add 'slv' ->...
View ArticleRename refactor bug in 2.24
Given this file:library ieee;use ieee.std_logic_1164.all;entity bug_test isport( clk :instd_logic; rst :instd_logic; test_one :instd_logic; test_two :instd_logic; test1_out :outstd_logic; test2_out...
View ArticleBug with overloaded function resolution in 2.24
Looks like overloaded functions are not properly resolved when used on the left side of a port map.read more
View ArticleProblems with eclipse 4.4.1 with sigasi 2.24
Hello, sigasi 2.24 seems to have some problems on eclipse 4.4.1. Here is what i did: download current eclipse (4.4.1) (64bit cpp)changed ini file (-Xmx512m to -Xmx1400m)installed sigasi in eclipse...
View ArticleWrong statemachine warning
Hi,statemachine transitions containing "after" keyword, produce warning message "Dead state "XXX": state does not have outgoing transitions". The following example reproduce this:type t_states...
View ArticleVerilog with macros
Hello, I just installed the verilog but the macros keyword "define" is not highlighed.. is this a problem in highlighting or the macros are not supported for the verilog or do I have to make any...
View Article*.sdc files in Quartus projects
It would be nice to see the Synopsis Design Constraint files (*.sdc) in the Project Explorer. While you're at it, add visibility for the *_hw.tcl files too?Regards,Josy
View ArticleFeature request: Coverage data view
Hi, These days I am working with VHDL verification, and one of the important tasks are closing in on 100% code coverage. I use Riviera-Pro, and use the "acdb report -html" to browse and examine the...
View ArticleError markings persist after undo
I've noticed that after performing an undo the editor doesn't always update error/warning markings. For example if I delete a semi-colon from the end of a line the editor marks the following line with...
View ArticleFeature Request: Missing Record Element Checking
It would be very useful to have errors checking when declaring record to ensure that all elements have been defined. Currently I don't see these errors until I compile. Something similar to missing...
View ArticleUser profile link missing
I had a hard time getting access to my userprofile under sigasi.com/user since I could not find any link to it on the site. Is that an oversight of me or is this a flaw in the page design?
View ArticleBug : Sigasi executes a batch file draggen into the editor insted of opening...
I noticed that if i dragged a windows .bat file into my editor windows in sigasi the file is executed insted of being opend for edit/viewing. Is this desired functionality?Regards Anders
View ArticleA question about TYPE declaration
While "playing" with type declaration in VHDL in Sigasi I found some interesting thing (see image attached). It`s interesting for me… is decimal_values type really physical?read more
View ArticleInstantiation of a component with a generic package as a generic
Hi,I was taking a look into the new features of VHDL-2008 and trying to modify some code to use them, like generic packages and passing packages into components as part of the generic. The following...
View Articletestbenches in Quartus project
this post is also related to: *.sdc files in Quartus projectsIf I create a test-bench in SIgasi it gets added to the Quartus project, which has the effect that when I compile the project Quartus will...
View ArticleSynchronize ISE Project and Sigasi projects
Is there a way to synchronize the Sigasi projects with a Xilinx ISE project? For a school project I work with a team and some of my colleagues want to stick with the default Xilinx ISE editor since...
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Updating Quartus II Projects - revisited
I never understood why Sigasi has to meddle with the Quartus II version. Sigasi wanting to upgrade Quartus II project In this particular case the actual project is being developed with QII 15.0, which...
View ArticleFormatting VHDL code - new option
hi have two things to suggest1. the thing i want to say is, no one can ever meet every coders needs, so adding a feature of "LOCK FORMATTING" (until designer "unlocks" it) will be extremely good and...
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