I use Sigasi also to modify the Xilinx constraints files because the Vivado editor is crap. It would be really nice to have some more features than just plain editing. I miss the support of TODO and FIXME tags. Also syntax highlighting would be really great. And maybe autocompletion :-)
Are there any plans to support the constraints files (XDC and UCF)?
I have a quartus project I have imported to Sigasi which includes some auto-generated Altera Qsys files. Sigasi generates quite a few warning messages about the auto-generated code. It would be nice to be able to waive rule checking on a particular file to suppress these warnings I don't care about.
I also thought about deleting the auto-generated files from my Sigasi project and replacing with an empty architecture equivalent, but Sigasi doesn't allow modifying the imported file list in this way.
Hi,
in a WHEN statement I usually use this format
data_out <= data_1 WHEN readw = one else
data_2 WHEN readw = two else
data_3 WHEN readw = tree else
(others => '0');
Is there an option to tell the auto-formatter to respect the lines?
Thank you
Igor
In many cases, signals assigned to port maps or to other signals are ordinary std_logic_vectors or other simple arrays.
Sigasi knows the type of these signals, since it is displayed in a tooltip when you hoover over the signal. The array indexes are displayed as well, so the size can be determined as well.
For these cases, it would be possible to add a check if the dimensions of the vectors match.
That would help pointing out errors, even before compilation is run.
When writing large comment blocks, it would be convenient if Sigasi put the "--" (or "--!" for Doxygen comments) automatically in the beginning of the line. Way of working would be as follows :
User types a "--" or "--!" at the beginning of the line, types something, and then presses enter.
If the line above is also a comment line, Sigasi automatically puts "--" or "--!" at the beginning of the new line.
If you have code like this:
architecture a1 of reformatTest is
beginwhen test_sig <='0'when rising_edge(tx_clk);
endarchitecture a1;
architecture a1 of reformatTest is
beginwhen test_sig <='0'when rising_edge (tx_clk);endarchitecture a1 ;
If I carry on working without noticing, then even when I fix the 'when' problem, reformatting doesn't put things back how th
I have been able to maintain most of my preferences with INI files fed to Sigasi as command line options, as follows:
sigasi --launcher.ini sigasi.ini
where the last line of the sigasi.ini file is, as follows:
-Declipse.pluginCustomization=defaults.ini
In the defaults.ini file, I can control preferences like the font:
org.eclipse.ui.workbench/org.eclipse.jface.textfont=1|Courier New|11.0|0|GTK|1|;
org.eclipse.ui.workbench/org.eclipse.ui.workbench.texteditor.blockSelectionModeFont=1|Courier New|11.0|0|GTK|1|;
or that I want the Sigasi hierarchy viewer have the instantiation f
Hi there,
is it possible to resolve calculations with real datatypes in sigasi?
Minimum example:
libraryIEEE;
useIEEE.STD_LOGIC_1164.all;
use work.math_pkg.all;
package test_pkg isconstant test :real:=1.0 / 2.0;
end test_pkg;
Unfortunatly the value which I can see if I hover over test is 0. (Calculation seems to be just in integer)
thanks in advance
I am having issues making the license work on an Arch Linux x86-64 installation.
The only error message that I get is this:
!ENTRY org.apache.log4j 2020140327 09:47:56.938 !MESSAGE com.sigasi.hdt.shared.ui.internal.fn.SigasiLicensePreferencePage – Sigasi Pro License: License isnot valid (Bad License String(Invalid Mac Address in key.
Hi
I use the auto-complete feature to instantiate components. I start always with a "ent" and hit CTRL + space. Sigasi then offers me to instantiate one of the components in my libraries. If I choose one Sigasi pastes the following code
adc_inst :entityENTITY work.adc
Any idea why it inserts the "entity" twice? I had to say that I use the "upperCaseKeywords" setting.
I can't simulate my design.
My friends are using the 64Bit Version. On their PCs It works after the update, but my PC is just a 32 Bit.
What can I do that it works?
Sometimes there's a compiler warning that we know is allright. It'd be nice if we could indicate that this is OK, so that the file isn't flagged with a warning (or error) icon any more.
In C-lint, you can indicate that something can be ignored by adding a comment at the end of the line, like : /*lint !e506 */
Maybe something similar can be done in Sigasi ? E.g. #!warn , or #!error or #!
Regards,
Marc
I'm testing the premium version of Sigasi and it looks very promising.
Hello,
when defining a function in the package head and implementating them in the package body, it is not possible to refactor the function parameter names. Refactoring the function name works well, but not the parameters.
Maybe this is a bug or a not implementated feature. If second is right, maybe it would make sense to implementate.
Best regards
Tobias Baumann
Hi there,
I'm writing new vhdl templates for my company. Since we're using subversion, we like to use svn keywords to automatically include several information like "LastChangedDate". This works fine until now.
But including these keywords into vhdl templates is not working. Sigasi prints out: "Invalid escape sequence '$'".
I think the code and picture is more self explaining
How can I solve the problem?
Thanks in advance.
Rob
/*! * \brief ${brief_description} * $HeadURL$ * $LastChangedRevision$ * $LastChangedBy$
Dear Sigasi users,
I set a color scheme for Sigasi. That is the one I would like to use at work at home at everywhere.
I can't find an option for save it.
If I copy the whole sigasi software with the set color settings to another PC it will use the default settings.
I would accept any solution except manually set all the different colors by mouse clicking.
Thanks in advance,
Zoltan
do you intend to provide a Sigasi release taking into account VHDL-AMS standard ?
and if yes, when do you think that it could be available ?
thank you by advance for your answer.
I'm using IP-Cores from the FPGA vendor (Lattice) and already included a 'black box library' for the usage of its components. Unfortunately I still get error messages e.g. within following code:
library xp2;configuration behav_xp2_tag_mem_con of xp2_tag_mem isfor behav_xp2_tag_mem forall:SSPIA useentity xp2.SSPIA(V);endfor;endfor;end behav_xp2_tag_mem_con;
The error messages are "Could not find declaration corresponding to 'SSPIA'." and "Could not find declaration corresponding to 'V'."
Hi,
After updating to v2.23 this morning, a number of 'incorrect' error markers were introduced to to my code base. Apparently they occur only around declarations with self-defined types.
I've added some screenshots snippets of error markers occurring with the self-defined type :
type t_slv_List is array (natural range <>) of std_logic_vector;
Screenshot_1
Screenshot_2
Hi!
I just downloaded Sigasi and I don't understand how to run my code. I go to 'run' menu and I can't find any option of running an existing code. What is the problem?