Hi,
Some of us prefer a black background for the editor. You can change all the syntax highlighting, but it is rather tedious.
It would be nice if you could just import a color scheme from a colleague.
Best regards,
Marc
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Feature request : load/save color schemes
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Small feature request: unused singal with attribute not flagged
unused declaration
Just a small detail: the attribute prevents a declaration from being flagged as 'unused'. Only if the attribute is removed, like in line 454, the expected warning is indicated.
Regards, Kurt
Found in Sigasi 2.23.1.20140729
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Where are the auto replace options?
I googled but found nothing on this. Where are the options for auto-replacing strings? I'd like to disable '..' -> '<=' since I use '…' a lot in my comments. I'd also like to add 'slv' -> 'std_logic_vector' and maybe some others.
Thanks,
Carl
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Rename refactor bug in 2.24
Given this file:
library ieee;
use ieee.std_logic_1164.all;
entity bug_test isport( clk :instd_logic; rst :instd_logic; test_one :instd_logic; test_two :instd_logic; test1_out :outstd_logic; test2_out :outstd_logic);
endentity bug_test;
architectureRTLof bug_test is
begin
test1_out <='1'when test_one ='0'and test_two ='1'else'0';
test_proc:process(clk, rst)
beginif rst ='1'then test2_out <='0';elsif rising_edge(clk)thenif test_one ='0'and test
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Bug with overloaded function resolution in 2.24
Looks like overloaded functions are not properly resolved when used on the left side of a port map.
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Problems with eclipse 4.4.1 with sigasi 2.24
Hello,
sigasi 2.24 seems to have some problems on eclipse 4.4.1.
Here is what i did:
- download current eclipse (4.4.1) (64bit cpp)
- changed ini file (-Xmx512m to -Xmx1400m)
- installed sigasi in eclipse (V2.24.0.201409020139 with optional features from http://download.sigasi.com/updates/eclipse-hdt2)
- restarted eclipse
- open tutorial project
- now i get a error message box:
Errors occurred during the build.Errors running builder 'Xtext Project Builder' on project 'aasdf'.
com.sigasi.hdt.vhdl.ui.builder.OptimizedClusteringBuilderState.queueAffectedResources(
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Wrong statemachine warning
Hi,
statemachine transitions containing "after" keyword, produce warning message "Dead state "XXX": state does not have outgoing transitions". The following example reproduce this:
type t_states is(STATE_A, STATE_B);signal states : t_states := STATE_A; test_process :process(states)begin case states iswhen STATE_A => states <= STATE_B;when STATE_B => states <= STATE_A after5ns;endcase; endprocess;
STATE_B produces the warning described above.
I'm using a Premium test license Version 2.25.
Best regards
Tobias
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Verilog with macros
Hello, I just installed the verilog but the macros keyword "define" is not highlighed.. is this a problem in highlighting or the macros are not supported for the verilog or do I have to make any changes to enable macros?
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*.sdc files in Quartus projects
It would be nice to see the Synopsis Design Constraint files (*.sdc) in the Project Explorer.
While you're at it, add visibility for the *_hw.tcl files too?
Regards,
Josy
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Feature request: Coverage data view
Hi,
These days I am working with VHDL verification, and one of the important tasks are closing in on 100% code coverage. I use Riviera-Pro, and use the "acdb report -html" to browse and examine the coverage tree with an external web browser.
I realize that it would be a huge advantage if Sigasi could read the coverage database, and highlight code lines depending on coverage status in some way.
I hope that you would consider functionality similar to this, in a future release.
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Error markings persist after undo
I've noticed that after performing an undo the editor doesn't always update error/warning markings. For example if I delete a semi-colon from the end of a line the editor marks the following line with an error, but if I perform an undo command (re-adding the semi-colon) the error marking sometimes doesn't go away.
I'm not sure what causes it to happen, but it seems to happen more often if I open another file and make changes to it before going back to the original file and performing the undo.
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Feature Request: Missing Record Element Checking
It would be very useful to have errors checking when declaring record to ensure that all elements have been defined. Currently I don't see these errors until I compile. Something similar to missing port mappings would be great:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package testPackage istype test_rec_type isrecord elem1 :std_logic; elem2 :std_logic;endrecord;constantTEST_CONST : test_rec_type :=-- Should have error here: "Missing element 'elem2'"( elem1 =>'1');
endpackage;
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User profile link missing
I had a hard time getting access to my userprofile under sigasi.com/user since I could not find any link to it on the site. Is that an oversight of me or is this a flaw in the page design?
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Bug : Sigasi executes a batch file draggen into the editor insted of opening it for edit...
I noticed that if i dragged a windows .bat file into my editor windows in sigasi the file is executed insted of being opend for edit/viewing.
Is this desired functionality?
Regards
Anders
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A question about TYPE declaration
While "playing" with type declaration in VHDL in Sigasi I found some interesting thing (see image attached).
It`s interesting for me… is decimal_values type really physical?
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Instantiation of a component with a generic package as a generic
Hi,
I was taking a look into the new features of VHDL-2008 and trying to modify some code to use them, like generic packages and passing packages into components as part of the generic. The following example works fine with questaSim 10.2c, but shows an error inside sigasi.
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testbenches in Quartus project
this post is also related to: *.sdc files in Quartus projects
If I create a test-bench in SIgasi it gets added to the Quartus project, which has the effect that when I compile the project Quartus will also try to Analyse/Synthesise the test-bench which doesn't always succeed … hmm, why? (rhetorical question)
Of course we want to see the test-bench in the SIgasi-project (otherwise we can't launch it …). And we 'd like to see the _hw.tcl and .sdc files (and possibly some other extensions?) too.
Regards,
Josy
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Synchronize ISE Project and Sigasi projects
Is there a way to synchronize the Sigasi projects with a Xilinx ISE project? For a school project I work with a team and some of my colleagues want to stick with the default Xilinx ISE editor since that is what they're familiar with. I love the features of Sigasi but I fail to see how I can synchronize the Xilinx ISE project with Sigasi. What should my workflow look like?
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Updating Quartus II Projects - revisited
I never understood why Sigasi has to meddle with the Quartus II version. 
Sigasi wanting to upgrade Quartus II project
In this particular case the actual project is being developed with QII 15.0, which is effectively newer. I didn't bother to update the setting in Sigasi(yet). If I decide to do this I will be rewarded with this MessageBox on about every other project I will open next. Eventually I will get confronted anyway at the rate I recompile those 'older' projects wit Quartus II 15.0 ,or higher .
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Formatting VHDL code - new option
hi have two things to suggest
1. the thing i want to say is,
no one can ever meet every coders needs, so adding a feature of "LOCK FORMATTING" (until designer "unlocks" it) will be extremely good and feasible.
so that, when i press CTRL + SHIFT + F it will format whole code, except the parts that i have "LOCKED"
(p.s. i know you can select the text and "CTRL + SHIFT + F" only that part, but that's not enough, from practice)
2.
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